In Cortex-M there are two fault address register, one for bus related errors and other for memory attributed errors and a single fault status register. Note: Though Classical series and Cortex-R has ...

compatible to ARMv7-M Instruction Set Architecture (Cortex-M3) ; single clock, static design ; single AMBA V2.0 AHB bus interface ; vectored interrupt controller ; enhanced instructions ; ...

Maintaining compatibility with the widely-used 32-bit ARM instruction set, each product in the Cortex-M series is positioned to meet a specific requirement, usually in regards to energy efficiency ...