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The L50(F) is a medium-sized, efficient 32-bit embedded RISC-V processor aimed at embedded systems with mid-range processing requirements. The core has a 5-stage pipeline. The L50F has a floating ...
IQonIC Works RV32IC_P5 Core is a larger, 5-stage pipeline core RISC-V processor, designed to meet the needs of medium-scale embedded applications that require higher performance, cache memories, and ...
The six-year-old RISC-V chipmaker secured an undisclosed sum from the Hong Kong Investment Corporation (HKIC), the government arm in charge of managing HK$62 billion (US$8 billion) of funds to ...
It’s an exciting time in the world of microprocessors, as the long-held promise of devices with open-source RISC-V cores is coming to fruition. Finally we might be about to see open-source from ...
The APXM-6200 core uses a 64-bit in-order implementation of the RISC-V architecture with an 11-stage pipeline ... It claims the APXM-6200 core has 2.5 greater performance density than the Cortex ...
Newly formed chip startup AheadComputing on Wednesday said it had raised $21.5 million in seed funding ... on the open source architecture called RISC-V, pronounced "risk five." ...