The eSi-SP-FP-Adder IP core implements single-precision (32-bit), IEEE 754 compliant, floating-point addition and subtraction operations. The number of pipeline stages is configurable to ... The ...

The Adder/Subtracter IP provides LUT and single DSP48 slice add/sub implementations. The Adder/Subtracter module can implement adders (A+B), subtracters (A–B), and dynamically configurable ... The ...