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1 个月
手把手教你用FPGA设计一个FIR数字滤波器
按照上述配置再生成50kHz、350kHz、450kHz频率的DDS。 生成完DDS后再生成一个fifo。该fifo用于跨时钟域,将DDS产生的10MHz时钟域的信号转到200MHz时钟域输入FIR进行滤波。fifo配置如下,深度16,数据位宽16bit。 最后将生成的IP核按下图连线,该dds用于测试fir滤波器。
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